isl 6262a 引脚定义详解

PGOOD - Power good open-drain output. Connect

externally with 680Ω to VCCP or 1.9kΩ to 3.3V.

电源良好PGOOD - 漏极开路输出。连
外部与680ΩVCCP或1.9kΩ至3.3V。

PSI# - Current indicator input. When asserted low, indicates

a reduced load-current condition and initiates single-phase

operation.

PSI＃ - 输入电流指示灯。当低电平时，表示
减少负载电流的条件，并启动单相
操作。

PMON - Analog output. PMON is proportional to the product

of Vsen and droop voltage.

PMON - 模拟输出。PMON的乘积成比例
VSEN和降电压。

RBIAS - 147k resistor to GND sets internal current

reference.

的RBIAS - 147K电阻到GND，设置内部电流
参考。

VR_TT# - Thermal overload output indicator with open-drain

output. Over-temperature pull-down resistance is 10Ω.

VR_TT＃ - 热过载漏极开路输出指示灯
输出。过温下拉电阻为10Ω。

NTC - Thermistor input to VRTT# circuit and a 60µA current

source is connected internally to this pin.

NTC - 热敏电阻输入VRTT＃电路和60μA电流
源内部连接到该管脚。

SOFT - A capacitor from this pin to GND sets the maximum

slew rate of the output voltage. SOFT is the non-inverting

input of the error amplifier.

SOFT - 从这个引脚GND的电容设定的最大
的输出电压的压摆率。软的非反相
误差放大器的输入端。

OCSET - Overcurrent set input. A resistor from this pin to

VO sets DROOP voltage limit for OC trip. A 10µA current

source is connected internally to this pin.

OCSET - 过电流设定输入。从这个引脚的电阻
VO设置的DROOP电压限制OC之旅。为10μA电流
源内部连接到该管脚。

VW - A resistor from this pin to COMP programs the

switching frequency (for example, 6.82kΩ ≅ 300kHz).

VW - 一个从针COMP计划的电阻
开关频率（例如，6.82kΩ≅为300kHz）

COMP - This pin is the output of the error amplifier

COMP - 此引脚是误差放大器的输出的

FB - This pin is the inverting input of error amplifier.

FB - 这个引脚是误差放大器的反相输入端。

FB2 - There is a switch between FB2 pin and the FB pin.

The switch is closed in single-phase operation and is

opened in two phase operation. The components connecting

to FB2 are to adjust the compensation in single phase

operation to achieve optimum performance.

FB2 - FB2引脚和FB引脚之间有一个开关。
开关关闭时，在单相操作和
在两相操作打开。这些组件连接
FB2是调整补偿的单相
操作，以达到最佳的性能。

VDIFF - This pin is the output of the differential amplifier.

VDIFF - 此引脚是差分放大器的输出端。

VSEN - Remote core voltage sense input.

的VSEN - 远程核心电压检测输入

RTN - Remote core voltage sense return.

RTN - 远程核心电压检测的回报

DROOP - Output of the droop amplifier. The voltage level on

this pin is the sum of VO and the droop voltage.

下垂 - 下垂放大器的输出。的电压电平
该引脚为VO和降电压的总和。

DFB - Inverting input to droop amplifier.

DFB - 下垂放大器的反相输入端。

VO - An input to the IC that reports the local output voltage.

VO - 输入到本机的输出电压的IC，报告。

VSUM - This pin is connected to the summation junction of

channel current sensing.

VSUM - 此引脚连接到求和结
通道电流检测。

VIN - Battery supply voltage. It is used for input voltage

feed-forward to improve input line transient performance.

电源电压VIN - 电池。它是用于输入电压
前馈，以提高输入线的瞬态性能。

GND - Signal ground. Connect to local controller ground.

GND - 信号地。连接到本地控制器地面。

VDD - 5V control power supply.

VDD - 5V的控制电源。

ISEN2 - Individual current sharing sensing for Channel 2. If

ISEN2 is pulled to 5V, phase 2’s gate signals are disabled.

ISL6262A is then configured in always-1-phase mode.

ISEN2 - 个人的电流共享传感通道2。如果
ISEN2被拉到5V，第2阶段的栅极信号被禁用。
ISL6262A，然后配置中始终-1相模式。

ISEN1 - Individual current sharing sensing for Channel 1.

ISEN1 - 个人电流共享传感通道1。

N/C - Not connected. Grounding this pin to signal ground in

the practical layout.

N / C - 未连接。该引脚接地，信号接地
实用的布局。

BOOT2 - This pin is the upper gate driver supply voltage for

phase 2. An internal boot strap diode is connected to the

PVCC pin.

BOOT2 - 此引脚上栅极驱动器电源电压
第2阶段。被连接到一个内部引导的肩带二极管
PVCC引脚。

UGATE2 - Upper MOSFET gate signal for phase 2.

UGATE2 - 第2期上MOSFET栅极信号。

PHASE2 - The phase node of phase 2. Connect this pin to

the source of the Channel 2 upper MOSFET.

PHASE2 - 第2阶段的阶段节点。该引脚连接到
通道2的上部MOSFET的源。

PGND2 - The return path of the lower gate driver for

phase 2.

PGND2 - 下部栅极驱动器的返回路径
第2阶段。

LGATE2 - Lower-side MOSFET gate signal for phase 2.

LGATE2 - 第2阶段的低侧MOSFET的栅极信号。

PVCC - 5V power supply for gate drivers.

PVCC - 5V栅极驱动器的电源。

LGATE1 - Lower-side MOSFET gate signal for phase 1.

LGATE1 - 第1阶段的低侧MOSFET的栅极信号。

PGND1 - The return path of the lower gate driver for

phase 1.

PGND1 - 下部栅极驱动器的返回路径
第1阶段。

PHASE1 - The phase node of phase 1. Connect this pin to

the source of the Channel 1 upper MOSFET.

PHASE1 - 第1阶段的阶段节点。该引脚连接到
的通道1上MOSFET的源。

UGATE1 - Upper MOSFET gate signal for phase 1.

UGATE1 - 第1阶段的上MOSFET栅极信号。

BOOT1 - This pin is the upper-gate-driver supply voltage for

phase 1. An internal boot strap diode is connected to the

PVCC pin.

BOOT1 - 此引脚上栅极驱动器电源电压
第1阶段。被连接到一个内部引导的肩带二极管
PVCC引脚。

VID0, VID1, VID2, VID3, VID4, VID5, VID6 - VID input with

VID0 is the least significant bit (LSB) and VID6 is the most

significant bit (MSB).

VID0，VID1，VID2，VID3，VID4，VID5，VID6 - VID输入
VID0是最少的有效位（LSB）和VID6是最
有效位（MSB）.

VR_ON - Digital enable input. A logic high signal on this pin

enables the regulator.

VR_ON - 数字使能输入。该引脚上的一个逻辑高电平信号
使稳压器。

DPRSLPVR - Deeper sleep enable signal. A logic high

signal on this pin indicates the micro-processor is in

deeper-sleep mode and also indicates a slow C4 entry or

exit rate with 41µA discharging or charging the SOFT

capacitor.

DPRSLPVR - 更深的睡眠使能信号。一个逻辑高电平
该引脚上的信号指示的微型处理器是在
更深的睡眠模式，并表示一个缓慢的C4项
退出率与41μA放电或充电的软
电容。

DPRSTP# - Deeper sleep slow wake up signal. A logic low

signal on this pin indicates the micro-processor is in

deeper-sleep mode.

DPRSTP＃ - 更深的睡眠唤醒信号缓慢。一个逻辑低电平
该引脚上的信号指示的微型处理器是在
更深的睡眠模式。

CLK_EN# - Digital output for system clock. Goes active 13

clks after Vcore is within 10% of Boot voltage.

CLK_EN - 数字输出作为系统时钟。去主动13
CLKS后，核心电压，启动电压的10％的范围内。

3V3 - 3.3V supply voltage for CLK_EN#.

3V3 - 3.3V电源电压CLK_EN＃。