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[原创] 故障现象:COMPAQ E500屏暗

songrui_2007 发表于 2007-5-17 14:32:02 | 显示全部楼层 |阅读模式 来自 中国江苏无锡

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解决方法:造成这种问题通常是高压板、屏线、或屏上的" p1 S, Z( F9 `  `9 S* n
被光灯损坏而造成的。用替换法替换背光灯管发现故障依
& G: x, I! `- H1 R& c& P旧,考虑问题出在高压板上,经测量发现高压板上的一个
* n, L9 {$ d( B+ }! w2 N, R线圈脱焊将其重新焊接问题解决。
songrui_2007  | 发表于 2007-5-17 14:34:02 | 显示全部楼层 来自 中国江苏无锡

DELL

Draft – Pong Adds/Cohiba Power Up Sequence3 b" v3 I( k! j. S, |. X" ]) h% }( t
Created: 11/06/00
- z- {& T8 O7 s7 ECreated for Armstrong/Riata by: C. Massery
4 b! r. X, m0 Z: {6 LEdited for Pong Adds/Cohiba by: Ty Kingsmore) B5 G# {/ w4 h) A* n& r
This document contains the power up sequence for the X00 rev of the Pong Adds/Cohiba platform.
2 S" ~# m+ t, k9 l  O: w5 cThere are two sections to this document. The first section lists notes for some of the signals listed in the waveform section. The
$ @' B* _3 c# Z9 h2 ~; V0 Asecond section shows a timing diagram of the power up sequence.
* W7 o9 o% g3 S6 E6 p7 iBelow are the conventions that are followed for the timing diagrams:
$ u) a7 `7 g- J7 G6 s2 q* W- time scale for x-axis is milli-seconds) s8 y8 M/ r* D) Z: [: G
- edge to edge relations of signals are to scale8 k8 U, J0 C' ]3 U  w* q
- signals that transition at the same time on the diagram occur within a relatively close time period
" [: g. Y, f$ ~3 [. P) o- invalid times are included for the rise time of voltage planes
2 O7 _6 s, x! Y; m& G- the timings are done based on a battery-boot situation.' O* Z' s: c& H) _7 H/ }) D
- The following configuration was used in taking the measurements:
; l- m9 p/ u7 s/ g  e- Pong Adds/Cohiba board 000E
" w! }* s* v& v# u# M- Sonny Q’s initial serial out’s BIOS
" }. F0 S. u" l$ C. T- NO video card2 _1 t! ~2 j, f  E( A( T
- LT charger board/ }* W2 Q3 o1 b' p
- 256 MB Samsung memory
! q' ?2 h6 R: Q  J# }: q- 933 CuT processor
/ e+ n  ^  @0 j, P1 Q. aWaveform Signal Information  ?6 ^( g& \  I5 F' K/ v
References below are to X00 revision of the schematic. This includes signal names, page and reference designator references.
  ~( B' m# ~! f  e* ~power_sw- source of this signal is JLED (p.35) or JDOCK (p.29); \  ?5 X% L$ B7 M5 Z
power_sw this signal is the output of the inverter U48, and the input to pin 2 of U80
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